1. Field of the Invention
The present invention relates to memory systems for computers, and more particularly to the design of a memory interface that automatically adjusts the timing between read data and an associated strobe signal returning from a memory during a read operation. The present invention also adjusts timing between the read data and an input driver enable signal.
2. Related Art
As processor speeds continue to increase, memory systems are under increasing pressure to provide data at faster rates. This has recently led to the development of new memory system designs. Memory latencies have been dramatically decreased by using page mode and extended data out (EDO) memory designs, which achieve a high burst rate and low latencies within a single page of memory. Another recent innovation is to incorporate a synchronous clocked interface into a memory chip, thereby allowing data from within the same page of memory to be clocked out of the memory chip in a continuous stream. Such memory chips with clocked interfaces are known as synchronous random access memories.
Recently, standards such as SyncLink and DDR have been developed to govern the transfer of data between memory and processor using such clocked interfaces.
SyncLink, which will be known as IEEE Standard 1596.7, specifies an architecture that supports a 64 M-bit memory with a data transfer rate of 1.6 gigabytes per second.
DDR is an acronym for Double Data Rate SDRAM; SDRAM is an acronym for Synchronous Dynamic Random Access Memory. During read operations., DDR memories return a bi-directional data strobe signal (or data clock signal) along with the data. The data is clocked into the processor (or memory controller) on both edges of the data strobe signal. This differs from conventional memory systems, which rely on the system clock to latch the data received during a read operation.
Designing an interface that receives a data strobe signal from a DDR memory during a read operation presents challenges because a certain amount of skew typically arises between the data signal and the data strobe signal. If this skew is large enough, a data strobe edge, which is used to latch the data signal, can move from the center of the xe2x80x9cdata eyexe2x80x9d of the data signal into a transitional region or into another data eye. This may cause spurious data to be latched during a read operation. Skew may additionally arise between the data signal and an enable signal for an input driver that is used to drive the data signal from a memory bus into a latch in the processor (or in the memory controller). This type of skew may also cause spurious data to be latched during read operations.
What is needed is a system that adjusts the temporal alignment between a data signal and an associated data strobe signal received from a memory during a read operation. Additionally, what is needed is a system that adjusts the temporal alignment between a data signal received during a read operation and an associated input driver enable signal.
One embodiment of the present invention provides a method for synchronizing a data signal and a data strobe signal received from a random access memory. The method operates by initiating a read operation by sending a target address to the random access memory. Next. the method receives a data signal from the random access memory containing data retrieved from the target address. This data signal is passed through an input driver into a register by asserting an enable signal on the input driver. This enable signal passes through a first programmable delay circuit that has been programmed with a first delay value before feeding into the input driver. At the same time, the method receives a data strobe signal from the random access memory. This data strobe signal is passed through a second programmable delay circuit that has been programmed with a second delay value and is then used to latch the data signal into the register.
One embodiment of the present invention further comprises programming the first programmable delay circuit with the first delay value, and programming the second programmable delay circuit with the second delay value.
One embodiment of the present invention further comprises determining the first delay value and the second delay value by performing test read operations using a plurality of different combinations of different first delay values and different second delay values. In a variation on this embodiment, the test read operations are performed by initialization code during a system boot process.
In one embodiment of the present invention, the first delay value includes a coarse delay component that specifies a coarse delay increment, and a fine delay component that specifies a fine delay increment.
In one embodiment of the present invention, the random access memory is comprised of a plurality of memory modules, wherein a different first delay value and a different second delay value are associated with each memory module. In this embodiment, the target address is examined to determine which memory module the target address is directed to in order to select an associated first delay value and an associated second delay value.
One embodiment of the present invention includes periodically measuring deviations in propagation delay through the first programmable delay circuit and/or the second programmable delay circuit relative to a system clock, and adjusting the first delay value and/or the second delay value, if necessary, to compensate for measured deviations.